TI Touch Screen Controller Replaces Five Chips from Original iPhone Design

 A glimpse into the world of touch screen controllers

by Jerico N. C. Garcia

What does the Apple iPhone 3GS have in common with your regular ticketing kiosk? How about the Nintendo DS handheld game console and a regular bank teller machine? All of these products use touch screen technology solutions in one form or another, as provided by the leading controller suppliers for the last several years.

It has been generally accepted that the term refers to the ability to interact physically with what is shown on a display, via touch or contact, using either a finger, hand, or pen. The popularity of this application is mainly due to its ease of use, as well as the intuitive interfaces enabled by its use. With a market forecasted to grow to $9 billion dollars by 2015 (from $3.6 billion in 2008), there has been a flurry of activity in this sector, with some analysts reporting over 170 suppliers in the supply chain today.

The most popular technology used in touch screens is the resistive 4-wire and 5-wire approach, due to low cost and simple interface electronics. There is also a recent notable increase in overall shipping of products based on the Projected Capacitive Touch or PCT approach. This technology is used by Apple, for its iPhone and iPod Touch, and others including the Samsung Pixon12 and Sony Ericsson Satio.

Looking closer at the perennial (can I say that?) media favorite, the Apple iPhone, touch screen development has undergone a radical change from the 2G all the way to the 3GS model. Back in the 2G era, the touch screen controller function was implemented using a number of ICs mounted on a single mini PCB. The ICs include Apple’s custom sensing IC (fabricated by Broadcom with die markings BCM5973A), a Texas Instruments (TI) driving IC (CD3238), an NXP MCU (LPC2221 – 32 bit ARM Core), a Hosonic crystal, and an ATMEL EEPROM. 

Figure 1  Front and Back of Touch Screen Board from the iPhone 2G

The second generation 3G did not have the miniPCB. Instead, the Sensing IC, MCU, EEPROM, and crystal were all incorporated into Broadcom’s BCM5974 touch screen controller IC, while TI’s CD3239 replaced the CD3238.

The latest iPhone 3GS model appears to have integrated all five of the 2G’s touch screen controller functions under a single custom IC, with package markings 343S0464. The die markings F761586C indicate that winning this high volume socket, and also the related iPod Touch and Magic Mouse sockets, is a coup for Texas Instruments. Getting the required functionality onto a single chip was facilitated by fabricating at 90 nm. In fact, TI has been gaining some other big socket wins in this industry, notably the Motorola DROID resistive touch screen (using TI’s TSC2046 4-wire touch screen controller with low voltage digital I/O).

Figure 2  iPhone 3GS Board Showing Single Chip for Touch Screen Control

Figure 3  Die Photograph of TI Touch Screen Controller Delayered to Bottom Metal Layer

What is most impressive is that each of these wins shows TI’s breadth of technology to serve this market. In the case of the iPhone, TI has delivered a chip that is over 50% digital and memory. In the Droid, TI won with a tried and true design that is almost entirely analog circuitry, and appears to be the same as the touch screen technology from TI's acquisition Burr-Brown that Chipworks analyzed 10 years ago; though we haven’t extracted any circuitry on today’s chip, you can see the layout is very similar.

Figure 4  Comparison of Burr-Brown ADS7846 and TI TSC2046 Touch Screen Controllers

Of course, now we have Apple's latest product launch, the question will be who wins the controller socket in the iPad?  This is a hot and heavy sector these days, and with new entrants like Synaptics getting the design win in the Google Nexus One, nothing can be taken for granted.

Am I the only one to spot this? NXP Has a Socket win in the iPad!

In all the hype since yesterday about the iPad, and the screen shots from the Apple video showing the app's processor, leading to speculation about whether it is designed by PASemi or not, or whether it has an ARM A7, A8, or A9 core; or whether it was fabbed by Samsung or not, nobody has commented on the other chip that was in view.  I've shown it below in our screen shot from the Apple video - if you squint, you can see the NXP logo upside-down on the outlined part:

So it appears that the one solid piece of information we have so far about the innards of the iPad is that NXP have got a socket win, likely for a power management part.  NXP had chips in the first iPhone, and in later products, so this continues their presence in the Apple BOM listing.

The other bit of information that you can infer from the image is that the processor package doesn't look like the package-on-package stack used for the processors + DRAM in iPhones and iPod Touch players up until now.  I guess in the iPad there's enough real estate for separate DRAM chips, so that bit of extra expense isn't needed.

Now we wait for a real one to tear down!

IEDM Next Week!

This has also been posted on our Chipworks Inside Angle blogsite.

In a few days time the great and the good of the electron device world will be gathering in Baltimore for the 2009 IEEE International Electron Devices Meeting.  To quote the conference lead release, “IEDM is the world’s premier forum for the presentation of applied research in microelectronic, nanoelectronic and bioelectronic devices.” 

From my perspective, focused on chips that have made it to production, it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years.

In the last few days I’ve gone through the advance program, and here’s my pick of what I want to try and get to, in more or less chronological order.  As usual there are overlapping sessions with interesting papers in parallel slots, but we’ll take the decision as to which to attend on the conference floor.

Monday morning we have the plenary session, and we get to the delegates’ papers after lunch.  Session 5 on memory technology is dominated by Numonyx, with three out of seven papers (5.1, 5.3, and 5.7), on their phase-change memory (PCM) technology. Since we looked at their 90-nm 128 Mb PCM part earlier this year, I’ll be sure to take those in, especially the last paper of the session which discusses their 45-nm 1-Gb part.

Tuesday morning there’s another bunch of memory papers; IBM continues (11.1) the scaling of their embedded trench DRAM to the 32-nm node; and in paper 11.6 Qualcomm and TSMC are looking at 45-nm MRAM. 

There is also a session on 3D technology, with TSMC (14.1) discussing through-silicon vias (TSVs), and a paper by Fujitsu et al (14.6) on ultra-thinning wafers down to 7 µm.  Back at Semicon West, Jerry Bautista of Intel put up this slide of their Terascale project packaging:

It probably doesn’t show too well in a web image, but the wafer in the cross-section at the bottom right is about eight microns thick.  And given Samsung’s recent announcement of 15-µm thick dice in eight-stack flash-memories, we’re in for some super-thin chips in the not too distant future.

In the afternoon there’s a special session of invited papers on the design issues created by advanced CMOS processing (also known as design-for-manufacturability, or DFM), something that we’ve noticed and commented on in the recent generations of chips.  In fact, this topic is hot enough that we’ve drafted a DFM report on the Intel 32-nm. Session speakers are from IBM, Intel, TSMC, and NEC, and others.

In parallel sessions we have a SWOT (strengths, weaknesses, opportunities, threats) analysis from IMEC of germanium as a channel material (19.3), and a Sony paper (22.8) on a 0.9-µm pitch image sensor, designing using a “constant-light-diffraction-scaling methodology”.

Come Wednesday, the last day of the conference doesn’t slow down.  The morning is filled with advanced CMOS papers, two from Intel (28.1 and 28.4), and others from the IBM consortium (28.2) and UMC (28.3).  I have to say I’m looking forward to the second Intel paper, to see if there’s any clarification on the NMOS stress mechanisms in their 2^nd generation HKMG process. 

After my blog back in October, I’ve come to the conclusion that we don’t have e-SiC; talking to other folks in the business, it seems that it’s still too difficult to get the carbon to stay in place in the silicon lattice; and we can’t see any carbon that is definitively associated with the source/drains.  Hopefully we’ll find out next week!

In another morning session 27, on 3D memory, there’s a joint Intel/Numonyx PCM paper, and an invited review paper by Al Fazio, also from Intel.

Even though folks tend to take off home in the afternoon, I shall be there until the bitter end - session 34 is on flash memory, with reliability papers by Samsung (34.2), Toshiba (34.4), and Macronix (34.6).  Parallel session 36 covers off the interconnect stack, with three NEC presentations of note (36.1 - with Toshiba, 36.4, and 36.5).

So as always, no peace for the curious!  And I have to blow my own trumpet a bit, since I will be hosting the annual Chipworks ‘Lunch and Learn’ across the courtyard at the Marriott on Monday December 7^th at 12.00 noon.  We’ll be discussing some of the year’s chips, likely the ATI/TSMC 40-nm part, maybe a Freescale/IBM 45-nm chip, and of course we’ll have some of the details we found in Intel’s 32-nm Westmere part.  For anyone that want to come along, registration is here, or at the door.

Update: we’re not the only ones hosting at the Marriott - Applied Materials is holding a symposium on the future of NAND flash on Tuesday evening, and ASM is having a lunch seminar on ALD on Wednesday.  It will be a busy conference - hope to see you there!

Analog Devices uses New Strategies to Build the ADXL346

Contributed by: St.J. Dixon-Warren

Analog Devices recently launched the digital ADXL346 3 mm x 3 mm x 0.95 mm thick, three-axis accelerometer. This device competes directly in the consumer electronics market with the Bosch SMB380, the STMicroelectronics LIS331DL, the Freescale MMA7660 and the Kionix KXSD9, which are also available in small footprint 3 mm x 3 mm packages.  Chipworks analysis suggests that the launch of this new device was made feasible by Analog Devices new MEMS foundry strategy.

Since the introduction of the ADXL50 in 1991, Analog has built their MEMS inertial sensors using their iMEMS technology, which cleverly integrated the micromechanical structures and ASIC circuitry on a single die. Both the 3 mm x 5 mm ADXL345, which was discussed recently in a posting on the MEMS Industry Group Blog, and 3 mm x 3 mm ADXL346 contain a separate MEMS and ASIC dies, and they thus represent a marked change in Analog Devices MEMS strategy.  This new strategy allows Analog to separate the MEMS chip design from the ASIC design. They can choose to have the ASIC fabricated at a foundry. Chipworks’ analysis has found that the ADXL346 contains the same MEMS die as the ADXL345. Analog Devices has used some clever engineering to fit the two dies into the smaller footprint ADXL346.

Figure 1 ADXL345 Package Top (3 mm x 5 mm)

Figure 2 ADXL346 Package Top (3 mm x 3 mm)

The corresponding plan-view x-ray photographs are shown in Figure 3 and Figure 4.  The footprint for the MEMS and ASIC dies inside the ADXL345 is 2.8 mm x 3.3 mm, which is too large to fit inside the 3 mm x 3 mm ADXL346 package.

Figure 3 ADXL345 Package X-Ray

Figure 4 ADXL346 Package X-Ray

Two strategies have been used to fit the MEMS and ASIC dies inside the ADXL346. First, Analog has designed a new, smaller ASIC die for the ADXL346. The ADXL345 uses the 1.37 mm x 2.17 mm XL345C ASIC, while the ADXL346 uses the 56% smaller 0.86 mm x 1.94 mm XL346 ASIC. As mentioned, both parts use the same 1.25 mm x 1.47 mm MEMS die.  These parameters are summarized in Table 1. 

Shrinking the ASIC appears to have been insufficient to fit the two dies into the 3 mm x 3 mm ADXL346 package, and hence Analog has also rotated the MEMS die 90° with respect to the ASIC inside the ADXL346 package and then wire bonded the MEMS die to the package substrate, rather than directly to the ASIC. The interconnection to the XL346 ASIC is through wiring in the package substrate. Only a ground wire to the MEMS die lid connects directly to the ASIC. Chipworks has not seen this strategy used previously.  The Bosch SMB380, the Freescale MMA7660 and the Kionix KXSD9 have the MEMS and ASIC mounted side-by-side with direct wire bond connections from the MEMS to the ASIC. The STMicroelectronics LIS331DL stacks the ASIC over the hermetic lid of the MEMS die (this strategy requires thinning the die to achieve a 1 mm thickness).

The rapid appearance of the smaller footprint ADXL346 a few months after the launch of the ADLX345, shows the benefit of Analog Devices new strategy. They were able to rapidly shrink the area of the ASIC, while keeping the MEMS die the same, thus achieving the smaller 3 mm x 3 mm package size required for the consumer electronics market.  It is worth noting that Analog was an early to the market, in 2006, with a three-axis accelerometer, the ADXL330, which was fabricated with their integrated iMEMS process and packaged in a 4 mm x 4 mm x 1.2 mm thick package. It would appear that the complexity of their integrated iMEMS process meant that they could not easily achieve a 3 mm x 3 mm x sub-1 mm thick package without changing their MEMS strategy.

Table 1 ADLX345 versus ADXL346 Comparison

Chipworks Reference Reports

• EXR-0910-802 Analog Devices ADXL346 3-Axis Accelerometer MEMS Exploratory Report
• MPR-0907-802 Analog Devices ADXL345 Digital Accelerometer MEMS Process Review
• MPR-0708-801 Bosch SMB380 Accelerometer MEMS Process Review Report
• EXR-0905-802 Freescale MMA7660FC 3-Axix Accelerometer MEMS Exploratory Report
• EXR-0902-811 Kionix KXSD9 3-axis Ultra low power digital accelerometer MEMS Exploratory Report
• MPR-0809-802 STMicroelectronics LIS331DL  Accelerometer MEMS Process Review
• PPR-0602-801 Analog Devices ADXL330 3-axis Accelerometer Process Review Report (MEMS)

Intel 32 nm Westmere Architecture in the Core i5 660 Displays Numerous Innovations

Recently we at Chipworks managed to get our hands on some of Intel’s hot (not to say smoking!) new 32-nm Clarkdale/Westmere microprocessors.  Needless to say they went straight into the lab, so that we could get a look at the changes from the 45-nm high-k, metal gate (HKMG) generation.

To be honest, I was expecting more or less a straightforward shrink of the earlier process, possibly with a lower-k intermetal dielectric; however, while it’s a bit speculative, I don’t think we can say that.

However, let’s start with some numbers.  At IEDM [1] last year, Intel announced a contacted gate pitch and M1 – M3 (1x) metal pitch of 112.5 nm; – we see ~113 nm, so the same, allowing for measurement error.  SRAM cell size was given as 0.17 µm², exactly what we have found.  The physical gate length was reduced from 35 nm in the 45-nm process to 30 nm in the new generation; the smallest we have found so far is ~28nm. (more...)

For the complete article please visit the Chipworks Inside Angle blog hosted on Semiconductor International.

To learn about or order the Chipworks Reports on this technology please visit the Intel 32 nm Westmere landing page.

Fig - 32 nm on left, 45 nm on right

Design for Manufacturing Paper Appears in IEEE Spectrum

Last week I was at the Custom Integrated Circuits Conference in San Jose, giving a paper on "Design-for-Manufacturing Features in Nanometer Logic Processes – A Reverse Engineering Perspective".  A few days before the conference, I was contacted by a sharp-eyed journalist from IEEE Spectrum who was curious about the paper, and in due course an article "New Chips Loaded With Dummy Parts" appeared on the Spectrum website.  It's a very readable explanation of what's going on in the business these days, so I reproduce it below.  Many thanks to Anne-Marie for her patience while I went through all of this stuff!

New Chips Loaded With Dummy Parts

Reverse-engineering firm reveals how "design for manufacturability" is changing the look of ICs